Digital computer systems typically comprise one or more processors coupled to a memory subsystem via a processor bus. The memory subsystem typically includes a memory controller coupled to one or more Synchronous Dynamic Random Access Memory (SDRAM) modules via a memory data bus and associated control signals. The memory controller is responsible for accepting memory load and store requests from the processor, interfacing with the SDRAMs to perform a load or store operation, and returning any data associated with the load operation from the SDRAMs back to the processor. The memory controller also has the task of managing memory bank timing, maximizing the utilization of the memory data bus, and prioritizing reads over writes, when possible.
In order to maximize performance in a computer system, it is important for the memory subsystem to provide both minimum read access latency and maximum memory bandwidth. Latency (i.e., cycle time) is the minimum interval between the initiation of a data request from the processor until data is first returned to the processor. Memory bandwidth is the amount of data that can be transferred in a fixed period of time. Maximum memory bandwidth is important to limit the queuing effects from high memory traffic. Queuing effects will increase latency, slowing computer system performance.
Memory is organized into banks and pages. A memory bank is a logical unit of memory in a computer system, the number of banks is determined by the DRAM technology employed. A bank can consist of pages, the number of pages determined by the column addresses bits employed. In SDRAM memory, a memory page is defined by the number of bits that can be accessed from one row address. Thus, the size of a page is determined by the number of column addresses. For example, a device with 10 column address pins has a page depth of 1024 bits.
SDRAMs can be operated in page mode, with many accesses to the same page, or non-page mode, where each memory access opens a bank, performs the memory access, and closes the bank with auto precharge. Commercial workloads have a high percentage of random accesses, so page mode does not provide any performance benefit, and in fact can actually decrease performance because of additional close page, precharge and access operations. In non-page mode, SDRAMs are designed for peak performance when consecutive accesses are performed to different banks. Address mapping to the SDRAMs is performed by the memory controller. The memory controller maps the addresses such that sequential accesses go to different memory banks.
In computer memory technology, RAS (row address strobe) is a signal sent to a dynamic random access memory (SDRAM) that tells it that an associated address is a row address. A data bit in the SDRAM is stored in a cell located by the intersection of a column address and a row address. A column address strobe (CAS) signal is used to validate the column address.
A read operation is performed by activating a memory bank (i.e., issuing a RAS with a bank ID), executing the read (i.e., issuing a CAS with READ), waiting the requisite number of cycles for the CAS latency (tCL), then data is burst from the SDRAM into the memory controller. The memory controller must wait several cycles for the row to precharge (i.e., the tRP time) before reactivating that bank.
Similarly, a write operation is performed by activating a memory bank (i.e., issuing a RAS with a bank ID), issuing a write command (i.e., issuing a CAS with WRITE), waiting the requisite number of cycles for the CAS latency (tCL), bursting the data from the memory controller to the SDRAMs, then waiting for the write recovery (i.e., the tWR time) as well as the row precharge time (tRP).
Both Single Data Rate (SDR) and Double Data Rate (DDR) SDRAMs have a minimum timing requirement between driving RAS and driving CAS. This timing requirement is called tRCD. To achieve minimum read access latency for a single access, the memory controller typically uses the minimum allowable time between driving RAS and CAS on a read access.
Early DRAMs had separate row and column address signals so there is no conflict between activating a bank and subsequently reading from that bank. With the invention of Synchronous DRAM's, the address signals for the row and column are multiplexed on the same control bus and qualified by the RAS and CAS, respectively. Thus, if a system has the same number of cycles required for a data transfer (i.e., burst length) as is required for the RAS to CAS latency (tRCD), a conflict is introduced between achieving minimum latency and maximum bandwidth.
Thus, there is a need for a DRAM control mechanism that dynamically adjusts DRAM tRCD (RAS to CAS delay) timings to provide optimal latency during both high and low periods of memory traffic.